The present invention relates to a semiconductor memory device and manufacturing method thereof, and more particularly to a semiconductor memory device and manufacturing method thereof capable of increasing cell capacitance by enlarging the effective area of a capacitor.
The development of large-scale memory devices is rapidly progressing, along with the development of semiconductor manufacturing techniques and expansion in the applied fields for a memory device. In particular, remarkable progress has been made in connection with a DRAM which achieves high packing density by forming an individual memory cell comprising a single capacitor and a single transistor. High-speed operation, high capacity and miniaturization of the DRAM can be realized by shrinking the individual unit area occupied by a memory cell, but this decreases cell capacitance and, in turn, lowers the memory cell's immunity to soft errors which impede reliable information storage.
Much research into increasing storable capacitance within an individual unit area has been reported, which plays an important role in reliable information storage, miniaturization, and expedient function of semiconductor devices.
Capacitor structures such as trench-type, stack-type, and combined stack/trench type are known to increase the storable capacitance in an individual unit cell. Particularly, the trench-type capacitor has characteristics superior to the stack-type with respect to greater capacitance, but has a higher soft error rate and higher leakage current, and it is more difficult to manufacture. The research on the stack-type capacitor has been actively pursued because it is easier to manufacture and has greater immunity to soft error in comparison to the trench-type capacitor.
FIGS. 1 through 4 are described in U.S. Pat. No. 4,974,040, entitled "Dynamic Random Access Memory Device and Manufacturing Method of Producing Same," which discusses a process for manufacturing a semiconductor memory device comprising a single-story stack-type capacitor.
As shown in FIG. 1, a field oxide layer 101 for separating an active region from an isolation region is formed in a semiconductor substrate 100. A gate electrode 5 is formed on semiconductor substrate 100. Source and drain region 7 and 8 are formed by doping an impurity in semiconductor substrate 100, using gate electrode 5 as a mask. Then, a first insulating layer 9 for insulating the gate electrode and etch-blocking is formed on the whole surface of a transistor consisting of the gate, drain, and source.
As shown in FIG. 2, first insulating layer 9 on semiconductor substrate 100 is etched by a photolithography process, thereby forming a contact hole 11.
As shown in FIG. 3, after forming a first conductive layer by depositing a conductive material on the whole surface of semiconductor substrate 100 having the transistor, a storage electrode pattern 15 is formed. Here, the conductive material, e.g., polycrystalline silicon doped with an impurity, is deposited to form the first conductive layer, and then storage electrode 15 is formed by applying a mask pattern to form the storage electrode pattern.
As shown in FIG. 4, a first dielectric film 16 and a plate electrode 17 are formed. Here, first dielectric film 16 is formed by thinly coating a dielectric material on the whole surface of storage electrode 15. Then, after forming a second conductive layer by depositing a conductive material, such as polycrystalline silicon doped with an impurity, on the whole surface of semiconductor substrate 100, plate electrode 17 is formed by applying a mask pattern.
The conventional semiconductor memory device having a stack-type capacitor manufactured according to the foregoing process has low parasitic transistor properties and strong immunity to soft error. However, since the capacitor area is confined to a small portion of an individual unit cell, it is difficult to increase the storage capacity. Also, when the surface area of the storage electrode is increased within the confined area in order to increase the storage capacity, the contact hole becomes deep in the region where the storage electrode is formed, which makes step-wise material coverage difficult and causes difficulty in metal processing due to the uneven topography of the capacitor.